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MCP1810 ? 2016 microchip technology inc. ds20005623a-page 1 features ? ultra-low quiescent current: 20 na (typical) ? ultra-low shutdown supply current: 1na(typical) ? 150 ma output current capability for v r 3.5v ? 100 ma output current capability for v r ? 3.5v ? input operating voltage range: 2.5v to 5.5v ? standard output voltages (v r ): 1.2v, 1.8v, 2.5v, 3.0v, 3.3v, 4.2v ? low dropout voltage: 380 mv maximum at 150 ma ? stable with 1.0 f ceramic output capacitor ? overcurrent protection ? space saving, 8-lead very thin plastic dual flat, no lead package, 2 x 2 mm body vdfn applications ? energy harvesting ? long-life, battery-powered applications ? smart cards ? ultra-low consumption ?green? products ? portable electronics package types for v r < 4.0v, sot-23 5-lead package is also available by request. description the MCP1810 is a 150 ma (for v r 3.5v), 100 ma (for v r ? 3.5v) low dropout (ldo) linear regulator that provides high-current and low-output voltages, while maintaining an ultra-low 20 na of quiescent current during device operation. in addition, the MCP1810 can be shut down for an even lower 1 na (typical) supply current draw. the MCP1810 comes in six standard fixed output-voltage versions: 1.2v, 1.8v, 2.5v, 3.0v, 3.3v and 4.2v. the 150 ma output current capability, combined with the low output-voltage capability, make the MCP1810 a good choice for new ultra-long-life ldo applications that have high-current demands, but require ultra-low power consumption during sleep states. the MCP1810 is stable with ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. only 1 f (2.2 f recommended) of output capacitance is needed to stabilize the ldo. the MCP1810 ultra-low quiescent and shutdown current allows it to be paired with other ultra-low current draw devices, such as microchip?s nanowatt extreme low power (xlp) technology devices, for a complete ultra-low power solution. MCP1810 2x2 vdfn* nc v out nc v in fb 1 2 3 4 8 7 6 5 nc shdn gnd * includes exposed thermal pad (ep); see table 3-1 . ep 9 ultra-low quiescent current ldo regulator
MCP1810 ds20005623a-page 2 ? 2016 microchip technology inc. typical application functional block diagram v in v out fb gnd MCP1810 load c in c out shdn + - esr v in shdn voltage reference v out fb + - gnd overcurrent shdn
? 2016 microchip technology inc. ds20005623a-page 3 MCP1810 1.0 electrical characteristics absolute maximum ratings ? input voltage, v in ............................................................................................................................... ......................+6.0v maximum voltage on any pin - .................................................................................................. ....(gnd - 0.3v) to +6.0v output short-circuit duration................................................................................................. . ...........................unlimited storage temperature ............................................................................................................ ................. -65c to +150c maximum junction temperature, t j ..................................................................................................................... +150c operating junction temperature, t j ......................................................................................................... -40c to +85c esd protection on all pins (hbm) ............................................................................................... ........................... 4kv ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability. ac/dc characteristics electrical specifications: unless otherwise noted, v in =v r +800mv ( note 1 ) , i out =1ma, c in =c out =2.2f ceramic (x7r), t a = +25c. boldface type applies for junction temperatures t j of -40c to +85c ( note 2 ) . parameters sym. min. typ. max. units conditions input operating voltage v in 2.7 ? 5.5 v 2.5 ? 5.5 vv r ? 1.8v, i out < 50 ma output voltage range v out 1.2 ? 4.2 v input quiescent current i q ?20 50 na v in =v r + 800 mv or 2.7v (whichever is greater) i out =0 input quiescent current for shdn mode i shdn ? 1 ? na shdn =gnd ground current i gnd ?200 290 a v in =v r + 800 mv or 2.7v (whichever is greater) i out = 150 ma, v r ? 3.5v i out = 100 ma, v r > 3.5v maximum continuous output current i out ?? 150 ma v r 3.5v ?? 100 ma v r ? 3.5v current limit i out ?350? ma v out =0.9xv r v r 3.5v ?250? ma v out =0.9xv r v r ? 3.5v output voltage regulation v out v r -4% ? v r +4% vv r <1.8v ( note 3 ) v r -2% ? v r +2% vv r 1.8v ( note 3 ) line regulation ? v out / (v out x ? v in ) -4 ? +4 %/v v in = v in(min.) to 5.5v i out =50ma ( note 1 ) note 1: the minimum v in must meet two conditions: v in ? v in(min) and v in ?? v r ? v dropout(max). 2: the junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is short enough such that the rise in junction temperature over the ambient temperature is not significant. 3: v r is the nominal regulator output voltage. v r = 1.2v, 1.8v, 2.5v, 3.0v, 3.3v or 4.2v. 4: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 3% below its nominal value that was measured with an input voltage of v in =v out(max) +v dropout(max) .
MCP1810 ds20005623a-page 4 ? 2016 microchip technology inc. load regulation ? v out /v out -3 1 +3 % v in =(v in(min) +v in(max) )/2 i out = 0.02 ma to 150 ma ( note 1 ) dropout voltage v dropout ?? 380 mv i out =150ma v r 3.5v ( note 4 ) ?? 280 mv i out =100ma v r > 3.5v ( note 4 ) shutdown input logic high input v shdn-high 70 ??%v in v in =v r + 800 mv or 2.7v (whichever is greater) i out =1 ma ( note 3 ) logic low input v shdn-low ?? 30 %v in v in =v r + 800 mv or 2.7v (whichever is greater) i out =1 ma ( note 3 ) ac performance output delay from shdn t or ?20? ms shdn = gnd to v in v out = gnd to 95% v r output noise e n ?0.48?v/ ? hz v in = 3.3v c in = c out = 2.2 f ceramic (x7r) v r = 2.5v, i out = 50 ma f = 1 khz ?48?vrms v in = 3.3v c in = c out = 2.2 f ceramic (x7r) v r = 2.5v, i out = 50 ma f = 100 hz to 1 mhz power supply ripple rejection ratio psrr ? 40 ? db f = 100 hz, i out =10ma v inac =200mv pk-pk c in =0f ac/dc characteristics (continued) electrical specifications: unless otherwise noted, v in =v r +800mv ( note 1 ) , i out =1ma, c in =c out =2.2f ceramic (x7r), t a = +25c. boldface type applies for junction temperatures t j of -40c to +85c ( note 2 ) . parameters sym. min. typ. max. units conditions note 1: the minimum v in must meet two conditions: v in ? v in(min) and v in ?? v r ? v dropout(max). 2: the junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. the test time is short enough such that the rise in junction temperature over the ambient temperature is not significant. 3: v r is the nominal regulator output voltage. v r = 1.2v, 1.8v, 2.5v, 3.0v, 3.3v or 4.2v. 4: dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 3% below its nominal value that was measured with an input voltage of v in =v out(max) +v dropout(max) .
? 2016 microchip technology inc. ds20005623a-page 5 MCP1810 temperature specifications parameters sym. min. typ. max. units conditions temperature ranges operating junction temperature range t j -40 ? +85 c steady state maximum junction temperature t j ? ? +150 c transient storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 2x2 mm vdfn-8ld ? ja ?73.1? c/wjedec ? standard fr4 board with 1 oz. copper and thermal vias ? jc ?10.7? c/w
MCP1810 ds20005623a-page 6 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005623a-page 7 MCP1810 2.0 typical performance curves note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-1: output voltage vs. input voltage (v r =1.2v). figure 2-2: output voltage vs. input voltage (v r =2.5v). figure 2-3: output voltage vs. input voltage (v r =3.3v). figure 2-4: output voltage vs. input voltage (v r =4.2v). figure 2-5: output voltage vs. load current (v r =1.2v). figure 2-6: output voltage vs. load current (v r =2.5v). note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.53.54.55.5 output voltage (v) input voltage (v) t j = +25c t j = -40c t j = +85c v r = 1.2v 2.490 2.495 2.500 2.505 2.510 2.515 2.53.54.55.5 output voltage (v) input voltage (v) t j = -40c t j = +25c t j = +85c v r = 2.5v 3.300 3.302 3.304 3.306 3.308 3.310 3.312 3.54.04.55.05.5 output voltage (v) input voltage (v) t j = +25c t j = +85c t j = -40c v r = 3.3v 4.185 4.190 4.195 4.200 4.205 4.210 4.5 4.7 4.9 5.1 5.3 5.5 output voltage (v) input voltage (v) t j = +25c t j = +85c t j = -40c v r = 4.2v 1.170 1.175 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 25 50 75 100 125 150 output voltage (v) load current (ma) t j = +85c t j = -40c t j = +25c v in = 2.5v v r = 1.2v 2.470 2.480 2.490 2.500 2.510 2.520 2.530 0 25 50 75 100 125 150 output voltage (v) load current (ma) v in = 3.3v t j = +25c t j = +85c t j = -40c v r = 2.5v
MCP1810 ds20005623a-page 8 ? 2016 microchip technology inc. note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-7: output voltage vs. load current (v r =3.3v). figure 2-8: output voltage vs. load current (v r =4.2v). figure 2-9: dropout voltage vs. load current (v r = 2.5v) figure 2-10: dropout voltage vs. load current (v r =3.3v). figure 2-11: dropout voltage vs. load current (v r =4.2v). figure 2-12: noise vs. frequency (v r =1.2v). 3.270 3.280 3.290 3.300 3.310 3.320 3.330 3.340 3.350 3.360 3.370 0 25 50 75 100 125 150 output voltage (v) load current (ma) v in = 4.1v t j = +25c t j = +85c t j = -40c v r = 3.3v 4.166 4.176 4.186 4.196 4.206 4.216 4.226 4.236 0 255075100 output voltage (v) load current (ma) v in = 5.0v t j = -40c t j = +25c t j = +85c v r = 4.2v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 255075100125150 dropout voltage (v) load current (ma) v r = 2.5v t j = +85c t j = -40c t j = +25c 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0 255075100125150 dropout voltage (v) load current (ma) v r = 3.3v t j = +25c t j = -40c t j = +85c 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0 20406080100 dropout voltage (v) load current (ma) v r = 4.2v t j = +25c t j = +85c t j = -40c 0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 output noise v/ hz frequency (khz) v r = 1.2v v in = 2.5v, c in = c out = 2.2 f i out = 50 ma noise (100 hz to 1 mhz) = 53.49 vrms
? 2016 microchip technology inc. ds20005623a-page 9 MCP1810 note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-13: noise vs. frequency (v r =2.5v). figure 2-14: noise vs. frequency (v r =3.3v). figure 2-15: noise vs. frequency (v r =4.2v). figure 2-16: power supply ripple rejection vs. frequency (v r =1.2v). figure 2-17: power supply ripple rejection vs. frequency (v r =2.5v). figure 2-18: power supply ripple rejection vs. frequency (v r =3.3v). 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 output noise v/ hz frequency (khz) v r = 2.5v v in = 3.3v, c in = c out = 2.2 f i out = 50 ma noise (100 hz to 1 mhz) = 47.57 vrms 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 output noise v/ hz frequency (khz) v r = 3.3v v in = 4.1v, c in = c out = 2.2 f i out = 50 ma noise (100 hz to 1 mhz) = 43.01 vrms 0.001 0.01 0.1 1 10 0.01 0.1 1 10 100 1000 output noise v/ hz frequency (khz) v r = 4.2v v in = 5.0v, c in = c out = 2.2 f i out = 50 ma noise (100 hz to 1 mhz) = 38.70 vrms -60 -50 -40 -30 -20 -10 0 10 0.01 0.1 1 10 100 1000 psrr (db) frequency (khz) v r = 1.2v c in = 0, c out = 2.2 f v in = 2.7v + 0.2 vpk-pk i out = 50 ma i out = 10 ma -60 -50 -40 -30 -20 -10 0 10 0.01 0.1 1 10 100 1000 psrr (db) frequency (khz) i out = 50 ma i out = 10 ma v r = 2.5v c in = 0, c out = 2.2 f v in = 3.5v + 0.2 vpk-pk -60 -50 -40 -30 -20 -10 0 10 0.01 0.1 1 10 100 1000 psrr (db) frequency (khz) i out = 10 ma i out = 50 ma v r = 3.3v c in = 0, c out = 2.2 f v in = 4.3v + 0.2 vpk-pk
MCP1810 ds20005623a-page 10 ? 2016 microchip technology inc. note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-19: power supply ripple rejection vs. frequency (v r =4.2v). figure 2-20: dynamic load step (v r =1.2v). figure 2-21: dynamic load step (v r =2.5v). figure 2-22: dynamic load step (v r =3.3v). figure 2-23: dynamic load step (v r =4.2v). figure 2-24: dynamic line step (v r =1.2v). -60 -50 -40 -30 -20 -10 0 10 0.01 0.1 1 10 100 1000 psrr (db) frequency (khz) i out = 50 ma i out = 10 ma v r = 4.2v c in = 0, c out = 2.2 f v in = 5.2v + 0.2 vpk-pk v out (ac coupled, 100 mv/div) 10 ma 100 a time = 80 s/div v r = 1.2v, v in = 2.7v, i out = 100 a to 10 ma i out (dc coupled, 5 ma/div) v out i out v out (ac coupled, 100 mv/div) 10 ma 100 a time = 80 s/div v r = 2.5v, v in = 3.3v, i out = 100 a to 10 ma i out (dc coupled, 5 ma/div) v out i out v out (ac coupled, 100 mv/div) 10 ma 100 a time = 80 s/div v r = 3.3v, v in = 4.1v, i out = 100 a to 10 ma i out (dc coupled, 5 ma/div) v out i out v out (ac coupled, 100 mv/div) 10 ma 100 a time = 80 s/div v r = 4.2v, v in = 5.0v, i out = 100 a to 10 ma i out (dc coupled, 5 ma/div) v out i out v out (ac coupled, 200 mv/div) time = 80 s/div v r = 1.2v, v in = 2.5v to 3.5v, i out = 10 ma 2.5v 3.5v v in (dc coupled, 1v/div) v in v out
? 2016 microchip technology inc. ds20005623a-page 11 MCP1810 note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-25: dynamic line step (v r =2.5v). figure 2-26: dynamic line step (v r =3.3v). figure 2-27: dynamic line step (v r =4.2v). figure 2-28: start-up from v in (v r = 1.2v). figure 2-29: start-up from v in (v r = 2.5v). figure 2-30: start-up from v in (v r = 3.3v). v out (ac coupled, 200 mv/div) time = 80 s/div v r = 2.5v, v in = 3.5v to 4.5v, i out = 10 ma 3.5v 4.5v v in (dc coupled, 1v/div) v in v out v out (ac coupled, 200 mv/div) time = 80 s/div v r = 3.3v, v in = 4.3v to 5.3v, i out = 10 ma 4.3v 5.3v v in (dc coupled, 1v/div) v in v out v out (ac coupled, 200 mv/div) time = 80 s/div v r = 4.2v, v in = 4.5v to 5.5v, i out = 10 ma 4.5v 5.5v v in (dc coupled, 1v/div) v in v out v out (dc coupled, 2v/div) time = 10 ms/div v r = 1.2v, v in = 0v to 2.7v, i out = 100 a 0v 2.7v v in (dc coupled, 2v/div) v in v out v out (dc coupled, 2v/div) time = 10 ms/div 0v 3.5v v in (dc coupled, 2v/div) v r = 2.5v, v in = 0v to 3.5v, i out = 100 a v in v out v out (dc coupled, 2v/div) time = 10 ms/div 0v 4.3v v in (dc coupled, 2v/div) v r = 3.3v, v in = 0v to 4.3v, i out = 100 a v in v out
MCP1810 ds20005623a-page 12 ? 2016 microchip technology inc. note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-31: start-up from v in (v r = 4.2v). figure 2-32: start-up from shdn (v r = 1.2v). figure 2-33: start-up from shdn (v r = 2.5v). figure 2-34: start-up from shdn (v r = 3.3v). figure 2-35: start-up from shdn (v r = 4.2v). figure 2-36: load regulation vs. junction temperature (v r = 1.2v). v out (dc coupled, 2v/div) time = 10 ms/div 0v 5.2v v in (dc coupled, 2v/div) v r = 4.2v, v in = 0v to 5.2v, i out = 100 a v in v out v out (dc coupled, 2v/div) time = 10 ms/div 0v 2.7v shdn (dc coupled, 2v/div) v r = 1.2v, v in = 2.7v, i out = 10 ma ~shdn v out v out (dc coupled, 2v/div) time = 10 ms/div 0v 3.3v v r = 2.5v, v in = 3.3v, i out = 10 ma shdn (dc coupled, 2v/div) ~shdn v out v out (dc coupled, 2v/div) time = 10 ms/div 0v 4.1v shdn (dc coupled, 2v/div) v r = 3.3v, v in = 4.1v, i out = 10 ma ~shdn v out v out (dc coupled, 2v/div) time = 10 ms/div 0v 5.0v shdn (dc coupled, 2v/div) v r = 4.2v, v in = 5.0v, i out = 10 ma ~shdn v out -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 -40-1510356085 load regulation (%) junction temperature (c) v in = 2.5v v in = 3.0v v in = 4.0v v in = 5.5v v r = 1.2v i out = 0 ma to 100 ma
? 2016 microchip technology inc. ds20005623a-page 13 MCP1810 note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-37: load regulation vs. junction temperature (v r = 2.5v). figure 2-38: load regulation vs. junction temperature (v r = 3.3v). figure 2-39: load regulation vs. junction temperature (v r = 4.2v). figure 2-40: line regulation vs. junction temperature (v r = 1.2v). figure 2-41: line regulation vs. junction temperature (v r = 2.5v). figure 2-42: line regulation vs. junction temperature (v r = 3.3v). -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 -40 -15 10 35 60 85 load regulation (%) junction temperature (c) v in = 3.0v v in = 4.0v v in = 5.5v v in = 5.0v v r = 2.5v i out = 0 ma to 100 ma -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 -40 -15 10 35 60 85 load regulation (%) junction temperature (c) v in = 3.5v v in = 4.1v v in = 5.0v v in = 4.5v v in = 5.5v v r = 3.3v i out = 0 ma to 100 ma 0.000 0.005 0.010 0.015 0.020 0.025 -40 -15 10 35 60 85 load regulation (%) junction temperature (c) v in = 5.5v v in = 4.6v v in = 5.0v v r = 4.2v i out = 0 ma to 100 ma 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -40-1510356085 line regulation (%/v) junction temperature (c) i out = 150 ma i out = 125 ma i out = 100 ma i out = 50 ma i out = 10 ma i out = 1 ma v r = 1.2v v in = 2.5v to 5.5v 0.17 0.18 0.19 0.20 0.21 0.22 0.23 0.24 0.25 0.26 0.27 -40 -15 10 35 60 85 line regulation (%/v) junction temperature (c) i out = 150 ma i out = 125 ma i out = 100 ma i out = 50 ma i out = 10 ma i out = 1 ma v r = 2.5v v in = 3.3v to 5.5v 0.150 0.155 0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 -40-1510356085 line regulation (%/v) junction temperature (c) i out = 150 ma i out = 125 ma i out = 100 ma i out = 50 ma i out = 1 ma i out = 10 ma v r = 3.3v v in = 4.1v to 5.5v
MCP1810 ds20005623a-page 14 ? 2016 microchip technology inc. note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-43: line regulation vs. junction temperature (v r = 4.2v). figure 2-44: quiescent current vs. input voltage (v r = 1.2v). figure 2-45: quiescent current vs. input voltage (v r = 2.5v). figure 2-46: quiescent current vs. input voltage (v r = 3.3v). figure 2-47: quiescent current vs. input voltage (v r = 4.2v). figure 2-48: ground current vs. junction temperature (v r = 1.2v). 0.14 0.15 0.16 0.17 0.18 0.19 0.20 -40 -15 10 35 60 85 line regulation (%/v) junction temperature (c) i out = 1 ma i out = 125 ma i out = 150 ma i out = 100 ma i out = 10 ma i out = 50 ma v r = 4.2v v in = 5.0v to 5.5v 4 6 8 10 12 14 16 18 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 quiescent current (na) input voltage (v) t j = 85c t j = 25c t j =-40c v r = 2.5v 4 6 8 10 12 14 16 18 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) t j = 85c t j = 25c t j =-40c v r = 2.5v 4 6 8 10 12 14 16 18 20 3.5 4.0 4.5 5.0 5.5 quiescent current (na) input voltage (v) t j = 85c t j = 25c t j = -40c v r = 3.3v 4 6 8 10 12 14 16 18 20 4.5 4.7 4.9 5.1 5.3 5.5 quiescent current (na) input voltage (v) t j = 25c t j = 85c t j = -40c v r = 4.2v 3.70 3.75 3.80 3.85 3.90 3.95 -40-1510356085 ground current (a) junction temperature (c) i out = 1 ma v r = 1.2v v in = 2.7v
? 2016 microchip technology inc. ds20005623a-page 15 MCP1810 note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-49: ground current vs. junction temperature (v r = 2.5v). figure 2-50: ground current vs. junction temperature (v r = 3.3v). figure 2-51: ground current vs. junction temperature (v r = 4.2v). figure 2-52: ground current vs. load current (v r = 1.2v). figure 2-53: ground current vs. load current (v r = 2.5v). figure 2-54: ground current vs. load current (v r = 3.3v). 4.55 4.60 4.65 4.70 4.75 4.80 4.85 4.90 -40 -15 10 35 60 85 ground current (a) junction temperature (c) i out = 1 ma v r = 2.5v 4.64 4.66 4.68 4.7 4.72 4.74 4.76 4.78 4.8 -40 -15 10 35 60 85 ground current (a) junction temperature (c) i out = 1 ma v r = 3.3v 4.65 4.70 4.75 4.80 4.85 4.90 4.95 -40 -15 10 35 60 85 ground current (a) junction temperature (c) i out = 1 ma v r = 4.2v 0 20 40 60 80 100 120 140 160 180 200 0 255075100125150 ground current (a) load current (ma) t j = 85c t j = -40c t j = 25c v r = 1.2v v in = 2.7v 0 20 40 60 80 100 120 140 160 180 200 220 240 0 25 50 75 100 125 150 ground current (a) load current (ma) t j = 25c t j = 85c t j = -40c v r = 2.5v v in = 3.3v 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 ground current (a) load current (ma) t j = 85c t j = -40c t j = 25c v r = 3.3v v in = 4.1v
MCP1810 ds20005623a-page 16 ? 2016 microchip technology inc. note: unless otherwise indicated, c out = 2.2 f ceramic (x7r), c in = 2.2 f ceramic (x7r), i out =1ma, t a =+25c, v in =v r + 0.8v, shdn =1m ? pull-up to v in . figure 2-55: ground current vs. load current (v r = 4.2v). figure 2-56: ground current vs. very low load current (v r = 1.2v). figure 2-57: ground current vs. very low load current (v r = 2.5v). figure 2-58: ground current vs. very low load current (v r = 3.3v). figure 2-59: ground current vs. very low load current (v r = 4.2v). 0 20 40 60 80 100 120 140 160 180 200 0 20406080100 ground current (a) load current (ma) t j = 85c t j = 25c t j = -40c v r = 4.2v v in = 5v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 1000 ground current (a) load current (a) v r = 1.2v v in = 2.7v t j = -40c t j = 25c t j = 85c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 1000 ground current (a) load current (a) v r = 2.5v v in = 3.3v t j = 85c t j = 25c t j =-40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 1000 ground current (a) load current (a) v r = 3.3v v in = 4.1v t j = 85c t j = 25c t j = -40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 1000 ground current (a) load current (a) v r = 4.2v v in = 5.0v t j = 85c t j = 25c t j = -40c
? 2016 microchip technology inc. ds20005623a-page 17 MCP1810 3.0 pin description the descriptions of the pins are listed in tab l e 3 - 1 . 3.1 ground pin (gnd) for optimal noise and power supply rejection ratio (psrr) performance, the gnd pin of the ldo should be tied to an electrically quiet circuit ground. this will help the ldo power supply rejection ratio and noise performance. the gnd pin of the ldo conducts only ground current, so a heavy trace is not required. for applications that have switching or noisy inputs, tie the gnd pin to the return of the output capacitor. ground planes help lower the inductance and voltage spikes caused by fast transient load currents. 3.2 regulated output voltage pin (v out ) the v out pin is the regulated output voltage of the ldo. a minimum output capacitance of 1.0 f is required for ldo stability. the MCP1810 is stable with ceramic, tantalum and aluminum-electrolytic capacitors. see section 4.2 ?output capacitor? for output capacitor selection guidance. 3.3 feedback pin (fb) the output voltage is connected to the fb input. this sets the output voltage regulation value. 3.4 input voltage supply pin (v in ) connect the unregulated or regulated input voltage source to v in . if the input voltage source is located several inches away from the ldo, or the input source is a battery, it is recommended that an input capacitor be used. a typical input capacitance value of 1 f to 10 f should be sufficient for most applications (2.2 f, typical). the type of capacitor used can be ceramic, tantalum, or aluminum-electrolytic. however, the low esr characteristics of the ceramic capacitor will yield better noise and psrr performance at high frequency. 3.5 shutdown control input (shdn ) the shdn input is used to turn the ldo output voltage on and off. when the shdn input is at a logic-high level, the ldo output voltage is enabled. when the shdn input is pulled to a logic-low level, the ldo output voltage is disabled. when the shdn input is pulled low, the ldo enters a low-quiescent current shutdown state, where the typical quiescent current is 1na. 3.6 exposed thermal pad (ep) the 2x2 vdfn 8-lead package has an exposed thermal pad on the bottom of the package. the exposed thermal pad gives the device better thermal characteristics by providing a good thermal path to either the printed circuit board (pcb) or heat sink, to remove heat from the device. the exposed pad of the package is at ground potential. table 3-1: pin function table MCP1810 2x2 vdfn name description 1 gnd ground 2v out regulated output voltage 3, 4, 5 nc not connected pins (should either be left floated or connected to ground) 6 fb output voltage feedback input 7v in input voltage supply 8 shdn shutdown control input (active-low) 9ep exposed thermal pad, connected to gnd
MCP1810 ds20005623a-page 18 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005623a-page 19 MCP1810 4.0 device overview the MCP1810 is a 150 ma/100 ma output current, low dropout (ldo) voltage regulator. the low dropout voltage of 380 mv maximum at 150 ma of current makes it ideal for battery-powered applications. the input voltage ranges from 2.5v to 5.5v. the MCP1810 adds a shutdown-control input pin and is available in six standard fixed-output voltage options: 1.2v, 1.8v, 2.5v, 3.0v, 3.3v and 4.2v. it uses a proprietary voltage reference and sensing scheme to maintain the ultra-low 20 na quiescent current. 4.1 output current and current limiting the MCP1810 ldo is tested and ensured to supply a minimum of 150 ma of output current for the 1.2v-to-3.5v output range, and 100 ma of output current for the 3.5v-to-4.2v output range. the device has no minimum output load, so the output load current can go to 0 ma and the ldo will continue regulating the output voltage within the specified tolerance. the MCP1810 also incorporates an output current limit. the current limit is set to 350 ma typical for the 1.2v ? v r 3.5v range, and to 250 ma typical for the 3.5v ? v r ? 5.5v range. 4.2 output capacitor the MCP1810 requires a minimum output capacitance of 1 f for output voltage stability. ceramic capacitors are recommended because of their size, cost and robust environmental qualities. aluminum-electrolytic and tantalum capacitors can be used on the ldo output as well. the output capacitor should be located as close to the ldo output as is practical. ceramic materials x7r and x5r have low temperature coefficients and are well within the acceptable esr range required. a typical 1 f x7r 0805 capacitor has an esr of 50 m ? . for extreme output currents - below 100 a or close to 150 ma/100 ma - an output capacitor with higher esr (tantalum, aluminum-electrolytic) is recommended. ceramic output capacitor may be used if a 0.5 ? to 1 ? resistor is placed in series with the capacitor. 4.3 input capacitor low input-source impedance is necessary for the ldo output to operate properly. when operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the ldo, some input capacitance is recommended. a minimum of 1.0 f to 4.7 f of capacitance is recommended for most applications. for applications that have output step load requirements, the input capacitance of the ldo is very important. the input capacitance provides a low-impedance source of current for the ldo to use for dynamic load changes. this allows the ldo to respond quickly to the output load step. for good step-response performance, the input capacitor should be equivalent or higher value than the output capacitor. the capacitor should be placed as close to the input of the ldo as is practical. larger input capacitors will also help reduce any high-frequency noise on the input and output of the ldo, as well as the effects of any inductance that exists between the input source voltage and the input capacitance of the ldo. 4.4 shutdown input (shdn ) the shdn input is an active-low input signal that turns the ldo on and off. the shdn threshold is a percentage of the input voltage. the maximum input-low logic level is 30% of v in and the minimum high logic level is 70% of v in . on the rising edge of the shdn input, the shutdown circuitry has a 20 ms (typical) delay before allowing the ldo output to turn on. this delay helps to reject any false turn-on signal or noise on the shdn input signal. after the 20 ms delay, the ldo output enters its current-limited soft-start period as it rises from 0v to its final regulation value. if the shdn input signal is pulled low during the 20 ms delay period, the timer will be reset and the delay time will start over again on the next rising edge of the shdn input. the total time from the shdn input going high (turn-on) to the ldo output being in regulation is typically 20 ms. figure 4-1 shows a timing diagram of the shdn input. figure 4-1: shutdown input timing diagram. shdn v out 20 ms 10 s t or 20 ns (typical)
MCP1810 ds20005623a-page 20 ? 2016 microchip technology inc. 4.5 dropout voltage dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 3% below the nominal value that was measured with a v r + 0.8v differential applied. the MCP1810 ldo has a low-dropout voltage specification of 230 mv (typical) for v r = 2.5v, 120 mv for v r = 3.3v at 150 ma out, and 70 mv (typical) for v r ? 4.2v at 100 ma out. see section 1.0 ?electrical characteristics? for maximum dropout voltage specifications.
? 2016 microchip technology inc. ds20005623a-page 21 MCP1810 5.0 application circuits and issues 5.1 typical application the MCP1810 is used for applications that require ultra-low quiescent current draw. figure 5-1: typical application circuit. 5.2 power calculations 5.2.1 power dissipation the internal power dissipation within the MCP1810 is a function of input voltage, output voltage, output current and quiescent current. equation 5-1 can be used to calculate the internal power dissipation for the ldo. equation 5-1: in addition to the ldo pass element power dissipation, there is power dissipation within the MCP1810 as a result of quiescent or ground current. the power dissipation as a result of the ground current can be calculated by applying equation 5-2 : equation 5-2: the total power dissipated within the MCP1810 is the sum of the power dissipated in the ldo pass device and the p(i gnd ) term. because of the cmos construction, the typical i gnd for the MCP1810 is maximum 290 a at full load. operating at a maximum v in of 5.5v results in a power dissipation of 1.6 mw. for most applications, this is small compared to the ldo pass device power dissipation, and can be neglected. the maximum continuous operating junction temperature specified for the MCP1810 is +85c . to estimate the internal junction temperature of the MCP1810, the total internal power dissipation is multiplied by the thermal resistance from junction-to-ambient (r ? ja ) of the device. the thermal resistance from junction to ambient for the 2x2 vdfn 8-lead package is estimated at 73.1c/w. equation 5-3: the maximum power dissipation capability for a package can be calculated given the junction-to-ambient thermal resistance and the maximum ambient temperature for the application. equation 5-4 can be used to determine the package maximum internal power dissipation. equation 5-4: v in v out fb gnd MCP1810 load c in c out shdn + - esr p ldo v in max ?? v out min ?? ? ?? i out max ?? ? = where: p ldo = internal power dissipation of the ldo pass device v in(max) = maximum input voltage v out(min) = ldo minimum output voltage i out(max) = maximum output current p ignd ?? v in max ?? i gnd ? = where: p i(gnd) = power dissipation due to the quiescent current of the ldo v in(max) = maximum input voltage i gnd = current flowing into the gnd pin t jmax ?? p total r ? ja ? t amax ?? + = where: t j(max) = maximum continuous junction temperature p total = total power dissipation of the device r ? ja = thermal resistance from junction to ambient t a(max) = maximum ambient temperature p dmax ?? t jmax ?? t amax ?? ? ?? r ? ja --------------------------------------------------- = where: p d(max) = maximum power dissipation of the device t j(max) = maximum continuous junction temperature t a(max) = maximum ambient temperature r ? ja = thermal resistance from junction to ambient
MCP1810 ds20005623a-page 22 ? 2016 microchip technology inc. equation 5-5: equation 5-6: 5.3 typical application examples internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation are calculated in the following example. the power dissipation as a result of ground current is small enough to be neglected. 5.3.1 power dissipation example example 5-1: 5.3.1.1 device junction temperature rise the internal junction temperature rise is a function of internal power dissipation and of the thermal resistance from junction to ambient for the application. the thermal resistance from junction to ambient (r ? ja ) is derived from eia/jedec standards for measuring thermal resistance. the eia/jedec specification is jesd51. the standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. the actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. refer to application note an792, ?a method to determine how much power a sot23 can dissipate in an application? (ds00792), for more information regarding this subject. example 5-2: 5.3.1.2 junction temperature estimate to estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. for this example, the worst-case junction temperature is estimated below: example 5-3: 5.3.1.3 maximum package power dissipation at +60c ambient temperature example 5-4: package package type = 2 x 2 vdfn 8-lead input voltage v in =3.3v5% ldo output voltage and current v out =2.5v i out =150ma maximum ambient temperature t a(max) =+60c internal power dissipation p ldo(max) =(v in(max) ? v out(min) )xi out(max) p ldo = ((3.3v x 1.05) ? (2.5v x 0.975)) x150ma p ldo = 0.154 watts t jrise ?? p dmax ?? r ? ja ? = where: t j(rise) = rise in the device junction temperature over the ambient temperature p d(max) = maximum power dissipation of the device r ? ja = thermal resistance from junction to ambient t j t jrise ?? t a + = where: t j = junction temperature t j(rise) = rise in the device junction temperature over the ambient temperature t a = ambient temperature t j(rise) =p total xr ? ja t j(rise) = 0.154w x 73.1c/w t j(rise) = 11.3c t j =t j(rise) +t a(max) t j = 11.3c + 60.0c t j =71.3c 2x2 vdfn 8-lead (73.1c/w r ? ja ): p d(max) = (85c ? 60c)/73.1c/w p d(max) = 0.342w
? 2016 microchip technology inc. ds20005623a-page 23 MCP1810 6.0 packaging information 6.1 package marking information 8-lead vdfn (2 x 2 mm) example part number code MCP1810t-12i/j8a a12 MCP1810t-18i/j8a a18 MCP1810t-25i/j8a a25 MCP1810t-30i/j8a a30 MCP1810t-33i/j8a a33 MCP1810t-42i/j8a a42 a12 256 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
MCP1810 ds20005623a-page 24 ? 2016 microchip technology inc. 0.05 c 0.05 c 0.10 c a b 0.05 c c seating plane 12 n 2x top view side view bottom view note 1 12 n 0.10 c a b 0.10 c a b 0.10 c microchip technology drawing c04-1207a sheet 1 of 2 2x for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: 8-lead very thin plastic dual flat, no lead package (j8a) - 2x2 mm body [vdfn] (datum b) (datum a) 2.00 2.00 b a d2 e2 e 2 e l (k) 8x b a (a3) a1 0.08 c 8x with 1.7x0.9 mm exposed pad
? 2016 microchip technology inc. ds20005623a-page 25 MCP1810 microchip technology drawing c04-1207a sheet 2 of 2 ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. 1. 2. 3. notes: pin 1 visual index feature may vary, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m 8-lead very thin plastic dual fla t, no lead package (j8a) - 2x2 mm body [vdfn] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height terminal width overall width terminal length exposed pad width terminal thickness pitch standoff units dimension limits a1 a b e2 a3 e l e n 0.50 bsc 0.20 ref 0.85 0.25 0.20 0.80 0.00 0.25 0.30 0.90 0.85 0.02 2.00 bsc millimeters min nom 8 0.95 0.35 0.30 0.90 0.05 max k 0.25 ref terminal-to-exposed-pad overall length exposed pad length d d2 1.65 2.00 bsc 1.70 1.75 with 1.7x0.9 mm exposed pad
MCP1810 ds20005623a-page 26 ? 2016 microchip technology inc. recommended land pattern dimension limits units optional center pad width optional center pad length contact pitch y2 x2 1.95 0.95 millimeters 0.50 bsc min e max contact pad length (x8) contact pad width (x8) y1 x1 0.70 0.30 microchip technology drawing c04-3207a nom 12 20 c contact pad spacing 2.10 contact pad to center pad (x8) g2 0.23 thermal via diameter v thermal via pitch ev 0.30 1.00 bsc: basic dimension. theoretically exact value shown without tolerances. notes: dimensioning and tolerancing per asme y14.5m for best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process 1. 2. for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: e c ev y2 x1 y1 ?v x2 ch g1 g2 silk screen contact pad to pad (x6) g1 0.20 8-lead very thin plastic dual flat, no lead package (j8a) - 2x2 mm body [vdfn] with 1.7x0.9 mm exposed pad
? 2016 microchip technology inc. ds20005623a-page 27 MCP1810 appendix a: revision history revision a (september 2016) ? original release of this document.
MCP1810 ds20005623a-page 28 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005623a-page 29 MCP1810 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. -xx output device voltage x/ temp. xx x package device: MCP1810t: ultra-low quiescent current ldo regulator, tape and reel standard output voltages*: 12 = 1.2v 18 = 1.8v 25 = 2.5v 30 = 3.0v 33 = 3.3v 42 = 4.2v *contact factory for other output voltage options temperature: i= -40 ? c to +85 ? c (industrial) package type: j8a = very thin plastic dual flat, no lead package, vdfn, 8-lead, with 1.7 x 0.9 mm exposed pad examples: a) MCP1810t-12i/j8a: tape and reel, 1.2v output voltage, industrial temperature 8-ld vdfn package b) MCP1810t-18i/j8a: tape and reel, 1.8v output voltage, industrial temperature, 8-ld vdfn package c) MCP1810t-25i/j8a: tape and reel, 2.5v output voltage, industrial temperature, 8-ld vdfn package d) MCP1810t-30i/j8a: tape and reel, 3.0v output voltage, industrial temperature, 8-ld vdfn package e) MCP1810t-33i/j8a: tape and reel, 3.3v output voltage, industrial temperature, 8-ld vdfn package f) MCP1810t-42i/j8a: tape and reel, 4.2v output voltage, industrial temperature, 8-ld vdfn package
MCP1810 ds20005623a-page 30 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005623a-page 31 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0978-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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